[News] TSMC Reveals N2 Nanosheet Details: 35% Power Savings, 15% Performance Gain, Densest SRAM Cell Yet

With its N2 (2nm-class) node beginning mass production in the latter half of 2025, TSMC revealed more details about it at the IEEE International Electron Device Meeting (IEDM) a couple of days ago. According to IEEE Spectrum and Tom’s Hardware, TSMC’s new 2nm technology delivers up to 15% faster performance or up to 35% greater energy efficiency compared to its current 3nm process, while also enhancing transistor density by 15%.

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These improvements are primarily driven by TSMC’s gate-all-around (GAA) nanosheet transistors, the N2 NanoFlex design-technology co-optimization (DTCO), and other advancements, as per Tom’s Hardware.

According to a report by Liberty Times, industry sources indicate that TSMC’s 2nm trial production yield has exceeded 60%, surpassing expectations.

It is worth noting that Samsung started initial production of its 3nm node applying GAA transistor architecture as early as in 2022. However, as per Android Police, though the second-generation 3nm process, SF3-3GAP, has been introduced, Samsung is rumored to be struggling with the node’s yield rate, which makes it challenging to manufacture the Exynos 2500 chips in-house currently.

Better Design Flexibility

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Citing TSMC’s Vice President of R&D and Advanced Technology Geoffrey Yeap, the IEEE Spectrum report notes that N2 represents the culmination of over four years of effort. Unlike FinFET transistors, which feature a vertical silicon fin at their core, nanosheet or gate-all-around transistors utilize a stack of narrow silicon ribbons, the report adds.

According to IEEE Spectrum, the key difference lies in the improved control over current flow and the flexibility to design a wider range of devices by adjusting the width of the nanosheets. In contrast, FinFETs could only vary device characteristics by increasing the number of fins. Nanosheets, however, allow for more nuanced variations, enabling designs equivalent to fractional fins, like 1.5 fins, providing better optimization for specific logic circuits.

Notably, the flexibility of nanosheet technology significantly impacts SRAM, the primary on-chip memory in processors, according to IEEE Spectrum. For several generations, the six-transistor SRAM cell has lagged behind other logic circuits in scaling advancements. However, N2 breaks this trend, achieving the densest SRAM cell to date—38 megabits per square millimeter, an 11% improvement over the N3 process, as noted by the report.

The Tom’s Hardware report suggests that N2 nanosheet transistors outperform FinFETs significantly in performance per watt, especially at low supply voltages of 0.5V to 0.6V. Optimizations in the process and device design enhance clock speeds by approximately 20% while reducing standby power consumption by up to 75% at 0.5V.

Additionally, the integration of N2 NanoFlex and multi-threshold voltage (multi-Vt) options offers greater design flexibility, enabling the creation of energy-efficient processors with high logic density, according to Tom’s Hardware.

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(Photo credit: TSMC)